Semiconductor memory apparatus with power-meshed structure
AssigneeHynix Semiconductor Inc.
InventorsBoo Ho JUNG, Jun Ho Lee, Hyun Seok Kim, Sun Ki Cho, Yang Hee Kim, Young Won Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.
Claims15
A semiconductor memory apparatus comprising:
- a memory bank having a plurality of cell mats;
- a plurality of power lines disposed in parallel over predetermined portions of the memory bank;
- a column control region disposed adjacent to a side of the memory bank, an edge line of the side of the memory bank is perpendicular to an extending direction of the plurality of power lines;
- and
- a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.
A semiconductor memory apparatus comprising:
- a plurality of banks delimited on a semiconductor substrate and each having a plurality of cell mats which are disposed in a matrix shape;
- a plurality of power lines disposed over predetermined portions of each of the plurality of banks;
- a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines;
- a plate electrode disposed between the semiconductor substrate and the plurality of power lines in each bank and extending over the column control region;
- and
- contact parts disposed over the column control region and electrically connecting the power lines with the plate electrode.
A semiconductor memory apparatus comprising:
- a plurality of banks delimited on a semiconductor substrate and each having a plurality of cell mats which are disposed in a matrix shape;
- a plurality of power lines disposed over predetermined portions of each of the plurality of banks;
- a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines;
- a plate electrode disposed between the semiconductor substrate and the plurality of power lines in each bank and extending over the column control region;
- a conductive pattern disposed on the same plane as the plate electrode and electrically isolated from the plate electrode;
- and
- contact parts disposed over the column control region and electrically connecting the power lines with the conductive pattern.
Dependencies are inferred from the claim text.