Output short to ground protection circuit
AssigneesPanasonic Corporation, Panasonic Semiconductor Asia Pte., Ltd.
InventorsWee Sien HONG, Weijie LI, Guo Lei YU
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Abstract
An output short to ground protection circuit protects an electronic device when it is short circuited to ground. The protection circuit has an NMOS transistor coupled to the output power transistor. A fixed voltage generator is connected to a gate terminal of the NMOS transistor. A first voltage clamping circuit and a second voltage clamping circuit are provided. The voltage clamping circuits are utilized so as to limit the current outputted by the output power transistor when the short circuit occurs.
Claims9
An output short to ground protection circuit for an electronic device having an output power transistor, an output terminal and a capacitor connected between the output terminal and a ground, said protection circuit comprising:
- an NMOS transistor having a drain terminal connected to a gate terminal of the output power transistor;
- a fixed voltage generator connected to a gate terminal of the NMOS transistor;
- a first voltage clamping circuit having a first terminal connected to the gate terminal of the output power transistor and a second terminal connected to a source terminal of the NMOS transistor;
- and
- a second voltage clamping circuit having a first terminal connected to said source terminal of said NMOS transistor and second terminal connected to the output terminal.
A method of protecting an electronic device from an output short circuit to ground condition by an output short to ground protection circuit, said electronic device having:
- an output power transistor;
- an output terminal;
- and a capacitor connected between the output terminal and a ground, and said output short to ground protection circuit having:
- an NMOS transistor having a drain terminal connected to a gate terminal of the output power transistor;
- a fixed voltage generator connected to a gate terminal of the NMOS transistor;
- a first voltage clamping circuit having a first terminal connected to the gate terminal of the output power transistor and a second terminal connected to a source terminal of the NMOS transistor;
- and a second voltage clamping circuit having a first terminal connected to said source terminal of said NMOS transistor and second terminal connected to the output terminal, the method comprising:
- biasing the gate terminal of said NMOS transistor with a potential so as to make the NMOS transistor turn off under normal working conditions;
- clamping a first potential between said output terminal and the source terminal of said NMOS transistor;
- clamping a second potential between said drain and source terminals of said NMOS transistor;
- and
- turning on of said NMOS transistor, thus disregarding the second clamp potential, when the output terminal is short circuited to ground.
Dependencies are inferred from the claim text.