Shift register circuit, display device, and method for driving shift register circuit
AssigneeSharp Kabushiki Kaisha
InventorsHideki Morii, Akihisa Iwamoto, Takayuki Mizunaga, Yuuki Ohta, Kei Ikuta
Life of this patent
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Abstract
In at least one embodiment, under a non-load condition of a first supply line for a first clock signal and a second supply line for a second clock signal, a fall time of a clock pulse of the first clock signal, which is supplied to the first supply line, is longer than that of the second clock signal, which is supplied to the second supply line.
Claims19
A shift register circuit in which (i) a first clock signal which is made up of at least one clock signal and (ii) a second clock signal which is made up of at least one clock signal, are supplied to said shift register circuit,
- said shift register circuit, comprising:
- a plurality of shift registers which are connected to each other in series,
- each of the plurality of shift registers receiving (i) a predetermined one of the first clock signal, which is to be transmitted to an output terminal of the each of the plurality of shift registers via a corresponding switching element and then outputted as a corresponding output signal and (ii) a predetermined one of the second clock signal, which serves as a signal for driving a first circuit included in the each of the plurality of shift registers,
- in a case where said shift register circuit serves as a load on first and second supply lines, via which the first clock signal and the second clock signal are respectively supplied,
- under a non-load condition of the supply lines, fall time of a clock pulse of the first clock signal, which is supplied via the first supply line, being longer than that of the second clock signal, which is supplied via the second supply line.
A method for driving a shift register circuit, comprising the steps of:
- supplying to the shift register circuit (i) a first clock signal which is made up of at least one clock signal and (ii) a second clock signal which is made up of at least one clock signal;
- and
- causing each of a plurality of shift registers which are connected to each other in series to receive (i) a predetermined one of the first clock signal, which is to be transmitted to an output terminal of the each of the plurality of shift registers via a corresponding switching element and then outputted as a corresponding output signal and (ii) a predetermined one of the second clock signal, which serves as a signal for driving a first circuit included in the each of the plurality of shift registers, p1 in a case where the shift register circuit serves as a load on first and second supply lines, via which the first clock signal and the second clock signal are respectively supplied,
- under a non-load condition of the supply lines, fall time of a clock pulse of the first clock signal, which is supplied via the first supply line, being longer than that of the second clock signal, which is supplied via the second supply line.
Dependencies are inferred from the claim text.