Phase frequency detector
AssigneeMimos Berhad
InventorsMahmoud Hammam, Ismail Nesreen, Shahiman Mohd.Sulaiman Mohd
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Abstract
The present invention relates to a phase frequency detector (PFD) (100) for use as one of the blocks in a phase-locked loop. The PFD of the present invention has zero dead zone, has a simpler structure with a minimum number of transistors and requires a smaller area. The PFD of the present invention does not use any inverter or delay gate as found in the conventional PFD. Instead, the PFD of the present invention utilises feedback transistors that save power and thus the PFD of the present invention is suitable to be used in low power applications.
Claims15
A phase frequency detector (100), comprising:
- (a). a first signal receiving means (110) including a first input terminal (112) to receive a first input signal and a second input terminal (114) to receive a second input signal;
- (b). a second signal receiving means (150) cross-coupled said first input terminal (112) to receive said first input signal;
- and said second input terminal (114) to receive said second input signal;
- (c). a first node (136) connected for charging or discharging depending on the signals received at said input terminals (112, 114);
- (d). a second node (166) connected for charging or discharging depending on the signals received at said input terminals (112, 114);
- (e). a first control logic circuit (140) for receiving a control signal output by said first node (136) and output a first signal to an output terminal (146);
- and
- (f). a second control logic circuit (170) for receiving a control signal output by said second node (166) and output a second signal to an output terminal (134);
- (g). a first feedback means (130) comprising a first feedback transistor (132) for receiving signals from said output terminal (134) of said second control logic circuit (170);
- (h). a second feedback means (160) comprising a second feedback transistor (162) for receiving signals from said output terminal (146) of said first control logic circuit (140).
A method for generating a first output signal and a second output signal corresponding to phase difference or frequency difference between a first input signal and a second input signal comprising the steps of:
- (a). receiving at least two input signals, a first input signal and a second input signal;
- (b). detecting an edge of said first input signal to generate a first output signal in response to said first input signal;
- and
- (c). detecting an edge of said second input signal to generate a second output signal in response to said second input signal
- wherein the pulse width difference between said first output signal and said second output signal represents the difference of said first and second input signals.
Dependencies are inferred from the claim text.