Method for Compensation of Process-Induced Performance Variation in a Mosfet Integrated Circuit

An automated method for compensating for process-induced variations in drive current in an integrated circuit design, the method comprising:

• analyzing selected transistors of the integrated circuit design, by determining drive current variations induced by layout neighborhood;
• and
• mutually offsetting, via a computer system, the following against each other:
• (i) any determined variations from varying a gate-to-gate spacing of the selected transistors in the integrated circuit design, (ii) any determined variations from varying a contact spacing of the selected transistors in the integrated circuit design;
• and (iii) any determined variations from varying a gate length of the selected transistors.

An automated method for compensating for process-induced variations in drive current in an integrated circuit design, comprising the steps of:

• analyzing selected transistors of the integrated circuit design, by determining drive current variations induced by layout neighborhood;
• and
• mutually offsetting, via a computer system, the following against each other:
• (i) any determined variations from varying a gate-to-gate spacing of the selected transistors in the integrated circuit design, (ii) any determined variations from varying a contact spacing of the selected transistors in the integrated circuit design;
• and (iii) any determined variations from varying a gate length of the selected transistors.

An automated method for compensating for process-induced variations in drive current in an integrated circuit design, the method comprising:

• analyzing selected transistors of the integrated circuit design, by determining drive current variations induced by layout neighborhood;
• and
• mutually offsetting, via a computer system, the following against each other:
• (i) any determined variations from varying a gate-to-gate spacing of the selected transistors in the integrated circuit design, (ii) any determined variations from varying a contact spacing of the selected transistors in the integrated circuit design;
• and (iii) any determined variations from varying a gate length of the selected transistors.

A system for compensating for process-induced variations in drive current in an integrated circuit design, comprising:

• a computer configured to execute the following:
• analyzing selected transistors of the integrated circuit design, by determining drive current variations induced by layout neighborhood;
• and
• mutually offsetting, via a computer system, the following against each other:
• (i) any determined variations from varying a gate-to-gate spacing of the selected transistors in the integrated circuit design, (ii) any determined variations from varying a contact spacing of the selected transistors in the integrated circuit design;
• and (iii) any determined variations from varying a gate length of the selected transistors.

A nontransitory computer medium with computer instructions that cause a computer to execute:

• analyzing selected transistors of the integrated circuit design, by determining drive current variations induced by layout neighborhood;
• and
• mutually offsetting, via a computer system, the following against each other:
• (i) any determined variations from varying a gate-to-gate spacing of the selected transistors in the integrated circuit design, (ii) any determined variations from varying a contact spacing of the selected transistors in the integrated circuit design;
• and (iii) any determined variations from varying a gate length of the selected transistors.