Generating Test Benches for Pre-Silicon Validation of Retimed Complex IC Designs Against a Reference Design

A method, comprising:

• parsing a hierarchy of an electrical reference model that comprises one or more reference modules;
• processing a description file that specifies relationships between ports of instances within an electrical design model and corresponding ports of the one or more reference modules of the electrical reference model, wherein the description file includes one or more names, wherein the one or more names respectively correspond to one or more implicit defines, wherein each of the one or more implicit defines includes a path through the hierarchy of the electrical reference model to a respective one of the one or more reference modules;
• and
• dependent on said processing, generating a test bench for verifying the electrical design module;
• wherein the test bench is computer-executable to:
• drive one or more input ports of the electrical design module with values presented to one or more corresponding ports of the electrical reference model;
• check, on a clock-cycle basis, one or more output ports of the electrical design model against one or more corresponding ports of the electrical reference model;
• and
• record, for each given one of the one or more output ports, an indication of whether the given output port matches a corresponding port of the electrical reference model.

A method, comprising:

• parsing an electrical reference model that comprises one or more reference modules, wherein the electrical reference model includes multiple levels of hierarchy;
• processing a description file that specifies relationships between ports of instances within an electrical design model and corresponding ports of the one or more reference modules of the electrical reference model;
• dependent upon the description file, generating a first test bench that instantiates one or more instances of the electrical design model, wherein the first test bench includes executable code that checks the one of more instances of the electrical design model against one or more reference modules located at a given level of hierarchy within the electrical reference model;
• and
• dependent upon the description file, generating a second test bench that instantiates the one or more instances of the electrical design model, wherein the second test bench includes executable code that checks the one of more instances of the electrical design model against one or more reference modules located at a different level of hierarchy within the electrical reference model;
• such that the first test bench and the second test bench are generated dependent on a same version of the description file.

A program storage device readable by a computing device that tangibly embodies a program of instructions executable by the computing device to:

• process a description file that specifies relationships between ports of instances within an electrical design model and corresponding ports of one or more reference modules of an electrical reference model, wherein the electrical reference model comprises one or more reference modules and includes multiple levels of hierarchy;
• dependent upon the description file, generate a first test bench that instantiates one or more instances of the electrical design model, wherein the first test bench includes executable code that checks the one of more instances of the electrical design model against one or more reference modules located at a given level of hierarchy within the electrical reference model;
• and
• dependent upon the description file, generate a second test bench that instantiates the one or more instances of the electrical design model, wherein the second test bench includes executable code that checks the one of more instances of the electrical design model against one or more reference modules located at a different level of hierarchy within the electrical reference model;
• such that the first test bench and the second test bench are generated dependent on a same version of the description file.