System and Method of Test Mode Gate Operation

An apparatus comprising:

• a circuit comprising a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element;
• wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate;
• wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element;
• wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode;
• and
• wherein, in the test mode, an output of the second gate element is fixed at a constant logic level.

An apparatus comprising:

• means for isolating a starting element and an ending element of a logic path;
• a first means for gating the starting element, wherein the first means for gating the starting element is coupled between the starting element and the means for isolating;
• a second means for gating the means for isolating the starting element and the ending element, wherein the second means for gating the means for isolating the starting element and the ending element is coupled between the ending element and the means for isolating the starting element;
• wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode;
• and
• wherein, in the test mode, an output of the second means for gating is fixed at a constant logic level.

A method comprising:

• a first step for receiving timing information related to a design of a circuit after a layout phase of generating the design of the circuit;
• a second step for selectively identifying at least one gate of a combinational logic portion of the design of the circuit to be modified to respond to a test enable signal, the at least one gate identified at least partially based on the timing information;
• and
• a third step for modifying the at least one gate, wherein the at least one modified gate is fixed at a constant level during a test mode and is dynamically changeable during a functional mode of operation of the circuit.

A computer readable medium storing instructions executable by a computer, the instructions comprising:

• instructions that are executable by the computer to receive timing information related to the design of the circuit after a layout phase of generating a design of a circuit;
• instructions that are executable by the computer to selectively identify at least one gate of a combinational logic portion of the design of the circuit to be modified to respond to a test enable signal, the at least one gate identified at least partially based on the timing information;
• and
• instructions that are executable by the computer to modify the at least one gate, wherein the at least one modified gate is fixed at a constant level during a test mode and is dynamically changeable during a functional mode of operation of the circuit.

A method comprising:

• receiving design information representing at least one physical property of a semiconductor device, the semiconductor device including a memory, a circuit comprising:
• a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element;
• wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate;
• wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element;
• wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode;
• and
• wherein, in the test mode, an output of the second gate element is fixed at a constant logic level;
• transforming the design information to comply with a file format;
• and
• generating a data file including the transformed design information.

A method comprising:

• receiving a data file including design information corresponding to a semiconductor device;
• and
• fabricating the semiconductor device according to the design information, wherein the semiconductor device includes:
• a circuit comprising:
• a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element;
• wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate;
• wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element;
• wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode;
• and
• wherein, in the test mode, an output of the second gate element is fixed at a constant logic level.

A method comprising:

• receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising:
• a circuit comprising:
• a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element;
• wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate;
• wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element;
• wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode;
• and
• wherein, in the test mode, an output of the second gate element is fixed at a constant logic level;
• and
• transforming the design information to generate a data file.

A method comprising:

• receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board;
• and
• manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises:
• a circuit comprising:
• a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element;
• wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate;
• wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element;
• wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode;
• and
• wherein, in the test mode, an output of the second gate element is fixed at a constant logic level.