Apparatus and method for testing semiconductor integrated circuits, and a non-transitory computer-readable medium having a semiconductor integrated circuit testing program
AssigneeFujitsu Semiconductor Limited
InventorsYusuke TANEFUSA, Kenichi GOMI, Satoshi YOKOO
Life of this patent
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Abstract
An apparatus for testing a semiconductor integrated circuit includes a pattern data generating unit configured to generate test pattern data for testing a write operation in a memory of the semiconductor integrated circuit; and a write unit configured to write the test pattern data into a storage area of the semiconductor integrated circuit.
Claims10
An apparatus for testing a semiconductor integrated circuit, the apparatus comprising:
- a pattern data generating unit that generates test pattern data for testing a write operation in a memory of the semiconductor integrated circuit;
- and
- a write unit that writes the test pattern data into a storage area of the semiconductor integrated circuit.
A method of testing a semiconductor integrated circuit by causing a computer to perform:
- generating test pattern data for testing a write operation in a memory of the semiconductor integrated circuit;
- and
- writing the test pattern data into a storage area of the semiconductor integrated circuit.
A non-transitory computer-readable recording medium having a computer-executable program for causing a computer to function as an apparatus for testing a semiconductor integrated circuit,
- the computer including:
- a first storage area in which test target information designating the semiconductor integrated circuit as a test target is stored;
- and
- a second storage area in which a non-operation condition table, an operation condition table, and a definition table are stored, wherein
- the non-operation condition table includes address information of all of the bits of a memory of the semiconductor integrated circuit and sets a non-operation condition for all of the bits,
- the operation condition table sets an operation condition for all of the bits, and
- the definition table associates LSI-identifying information that identifies the semiconductor integrated circuit with bit-specifying information that specifies an operation target bit of the memory,
- the computer-executable program causing the computer to perform
- acquiring operation target bit information corresponding to the test target information stored in the first storage area from the definition table;
- acquiring an operation condition for the operation target bit information from the operation condition table;
- merging the operation condition for the operation target bit information with the non-operation condition table in order to generate test pattern data;
- and
- writing the test pattern data into a storage area of the semiconductor integrated circuit.
Dependencies are inferred from the claim text.