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US 2011/0219274 A1Published application
Memory system and method for preventing system hang
AssigneeSamsung Electronics Co., Ltd.
InventorsBeom-Sig Cho, Jung-Joon Lee
Life of this patent
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Abstract
A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.
Claims28
A memory system, comprising:
- at least one memory device configured to receive a clock signal and an operating voltage to operate;
- and
- a memory controller including an error detection circuit having an error counter to determine a bit error rate (BER) based on the number of bit errors occurring in data transmitted between the memory controller and the at least one memory device, and configured to output a first control signal to change a frequency of the clock signal when a determined BER exceeds a first reference BER.
A memory system, comprising:
- at least a first semiconductor memory unit configured to use a clock signal and an operating voltage to operate;
- and
- at least one error detection circuit configured to determine a bit error rate (BER) for the first semiconductor memory unit based on a number of bit errors per data transmitted,
- wherein the memory system is configured to, in response to the BER reaching a threshold BER value, change at least one of a frequency of the clock signal and a voltage level of the operating voltage.
1 more element
A method of controlling a bit error rate (BER) in a memory system, the method including:
- (a) monitoring a bit error rate;
- (b) determining if the bit error rate exceeds a first threshold value;
- and
- (c) after it is determined that the bit error rate exceeds the first threshold value, performing one or more of:
- (1) lowering a frequency of a clock signal used for a semiconductor memory unit of the memory system, and (2) raising a voltage level of an operating voltage used in the semiconductor memory unit.
2 more elements
Dependencies are inferred from the claim text.