Information processing unit including smt-enabled cpu and its power consumption reduction method
AssigneeNEC Corporation
InventorHIROKI ARAI
Life of this patent
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AssigneeNEC Corporation
InventorHIROKI ARAI
Estimating the term…
An information processing unit includes a processing unit including a plurality of processor cores; and a power consumption reduction device configured to reduce power consumption of the processing unit. The power consumption reduction device measures the loads on threads that are running in the plurality of cores; checks the number of high load threads which are threads in a high load state and the number of low load threads which are threads in a low load state for each core, on the basis of the measuring results; selects, when there exists a core having high load threads whose number is less than a preset threshold on the number of high load threads, the core as a candidate core; and replaces the high load threads existing in the candidate core with the low load threads existing in other cores when the total number of the low load threads in a core other than the candidate core is not less than the number of the high load threads in the candidate core.
An information processing unit comprising:
A power consumption reduction method for reducing power consumption of a processing unit including a plurality of processor cores in an information processing unit, the method comprising:
A non-transitory computer-readable medium stored therein a program for enabling a computer to execute a power consumption reduction method for reducing power consumption of a processing unit including a plurality of processor cores in an information processing unit, the method comprising:
Dependencies are inferred from the claim text.