Dynamic warp subdivision for integrated branch and memory latency divergence tolerance
OwnerKevin Skadron, Jiayuan Meng +1inventors
InventorsKevin Skadron, Jiayuan Meng, David Tarjan
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Abstract
Dynamic warp subdivision (DWS), which allows a single warp to occupy more than one slot in the scheduler without requiring extra register file space, is described. Independent scheduling entities also allow divergent branch paths to interleave their execution, and allow threads that hit in the cache or otherwise have divergent memory-access latency to run ahead. The result is improved latency hiding and memory level parallelism (MLP).
Claims24
A method for use in a warp processing system, the warp processing system employing dynamic warps, each warp comprising a plurality of respective threads spawned as a consequence of a single instruction fetch, the method comprising the steps of:
- spawning a warp;
- responding to a first branch divergence having first and second branch paths by dividing the warp into first and second active warp-splits, the first warp-split representing respective threads that fall into the first branch path, the second warp-split representing respective threads that fall into the second branch path;
- and
- interleaving computation of the first and second branch paths.
A method for use in a warp processing system, the warp processing system employing dynamic warps, each warp comprising a plurality of respective threads spawned as a consequence of a single instruction fetch, the system having a cache, memory references to the cache variously defining cache hits and cache misses, the method comprising the steps of:
- spawning a warp;
- responding to a first memory latency divergence defined by the event of at least one cache miss by at least one of the respective threads of the warp by dividing the warp into first and second active warp-splits, the first warp-split representing respective threads that hit the cache, the second warp-split representing one or more respective threads that missed the cache;
- and
- continuing computation of at least the first warp-split.
A single instruction, multiple data organization system disposed to employ dynamic warps, each warp comprising a plurality of respective threads spawned as a consequence of a single instruction fetch, the system comprising:
- means responsive to a first branch divergence having first and second branch paths for dividing a warp into first and second active warp-splits, the first warp-split representing respective threads that fall into the first branch path, the second warp-split representing respective threads that fall into the second branch path;
- and
- means interleaving computation of the first and second branch paths.
A single instruction, multiple data organization system disposed to employ dynamic warps, each warp comprising a plurality of respective threads spawned as a consequence of a single instruction fetch, the system comprising:
- means responsive to a first memory latency divergence defined by the event of at least one cache miss by at least one of the respective threads of a warp for dividing the warp into first and second active warp-splits, the first warp-split representing respective threads that hit the cache, the second warp-split representing one or more respective threads that missed the cache;
- and
- means continuing computation of the first warp-split.
Dependencies are inferred from the claim text.