Semiconductor integrated circuit and register address controller
AssigneePanasonic Corporation
InventorsYuusuke ADACHI, Eiji Nagata
Life of this patent
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Abstract
This invention provides with a semiconductor integrated circuit, comprising a register map that makes correspondence between a register to which a CPU accesses and an address which specifies the register, wherein the register map includes a plurality of register maps in which assignments of address bits are rearranged in correspondence with each of a plurality of modes, and wherein any of the register maps is selected from the plurality of register maps according to the respective modes.
Claims15
A semiconductor integrated circuit, comprising:
- a register map that makes correspondence between a register to which a CPU accesses and an address which specifies the register;
- wherein the register map includes a plurality of register maps in which assignments of address bits are rearranged in correspondence with each of a plurality of modes;
- and
- wherein any of the register maps is selected from the plurality of register maps according to the respective modes.
A register address controller, comprising:
- a register where address information is to be set;
- and
- an address information setting unit configured to set the address information on the register.
A register address controller comprising:
- a register on which address information and bit information are to be set;
- and
- an address bit information setting unit configured to set the address information and the bit information on the register.
Dependencies are inferred from the claim text.