System on Chip Breakpoint Methodology

A system-on-chip (SoC) with debugging capability, the system-on-chip comprising:

• a central processing unit (CPU);
• a plurality of computing elements operatively connected to said CPU, wherein the CPU is configured to program said computing elements with task descriptors and said computing elements are configured to receive said task descriptors and to perform a computation based on the task descriptors, wherein the task descriptors include a field which specifies a breakpoint state of the computing element;
• and
• a system level event status register (ESR) operatively attached to and accessible by said CPU and said computing elements;
• wherein each of said computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state, wherein the computing element is configured to drive a breakpoint event to said event status register (ESR) if the present state of the computing element is the breakpoint state;
• wherein each of said computing elements has a halt logic unit operatively attached thereto, wherein said halt logic unit is configured to halt operation of the computing element, wherein said ESR is configurable to drive a breakpoint event to said halt logic units so that at least one of the computing elements is halted other than the computing element driving said breakpoint event.