Processor and memory control method
AssigneesSamsung Electronics Co., Ltd., Seoul National University Industry Foundation
InventorsIl Hyun Park, Soojung Ryu, Dong-Hoon Yoo, Dong Kwan Suh, Jeongwook Kim, Choon Ki Jang
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Abstract
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
Claims20
A processor comprising:
- a processor core;
- a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core;
- and
- a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
A memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:
- analyzing a characteristic of at least one of a load instruction and a store instruction executed in the processor core;
- allocating the at least one of the load instruction and the store instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic;
- and
- processing the at least one of the allocated load instruction and the allocated store instruction.
A computer-readable storage medium having stored therein program instructions for implementing a memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:
- analyzing a characteristic of at least one of a load instruction and a store instruction executed in the processor core;
- allocating the at least one of the load instruction and the store instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic;
- and
- processing the at least one of the allocated load instruction and the allocated store instruction.
Dependencies are inferred from the claim text.