System and method for managing self-refresh in a multi-rank memory
AssigneeMicron Technology, Inc.
InventorTodd D. Farrell
Life of this patent
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Abstract
Multi-rank memories and methods for self-refreshing multi-rank memories are disclosed. One such multi-rank memory includes a plurality of ranks of memory and self-refresh logic coupled to the plurality of ranks of memory. The self-refresh logic is configured to refresh a first rank of memory in a self-refresh state in response to refreshing a second rank of memory not in a self-refresh state in response to receiving a non-self-refresh refresh command for the second rank of memory.
Claims24
A method for performing self-refresh in a multi-rank memory, comprising:
- receiving a self-refresh command for a designated rank of memory;
- preventing the designated rank of memory from responding to non-self-refresh exit commands;
- refreshing at least one other rank of memory;
- and
- refreshing the designated rank of memory in response to refreshing the at least one other rank of memory.
A method for self-refreshing a rank of memory of a multi-rank memory, comprising:
- disabling at least one input signal buffer of the rank of memory;
- and
- refreshing both the rank of memory to be self-refreshed and another rank of memory not to be self-refreshed in response to a refresh command directed to the another rank of memory not to be self-refreshed.
A multi-rank memory, comprising:
- a plurality of ranks of memory;
- and
- self-refresh logic coupled to the plurality of ranks of memory and configured to refresh a first rank of memory in a self-refresh state in response to refreshing a second rank of memory not in a self-refresh state in response to receiving a non-self-refresh refresh command for the second rank of memory.
A multi-rank memory, comprising:
- a plurality of ranks of memory;
- an input/output (I/O) buffer coupled to the plurality of ranks of memory, the I/O buffer configured to provide memory signals to the plurality of ranks of memory for operation in response to receiving memory commands, the I/O buffer including self-refresh logic configured to enable refreshing of both first and second ranks of memory in response to a refresh command for the second rank of memory during a self-refresh state of the first rank of memory.
Dependencies are inferred from the claim text.