US 2011/0219171 A1Published application

Virtual channel support in a nonvolatile memory controller

Assignee248 SolidState, Inc

InventorsReinhard Kuehne, Vivian Chou

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Abstract

A controller uses N dedicated ports to receive N signals from N non-volatile memories independent of each other, and uses a bus in a time shared manner to transfer data to and from the N non-volatile memories. The controller receives from a processor, multiple operations to perform data transfers, and stores the operations along with a valid bit set active by the processor. When a signal from a non-volatile memory is active indicating its readiness and when a corresponding operation has a valid bit active, the controller starts performance of the operation. When the readiness signal becomes inactive, the controller internally suspends the operation and starts performing another operation on another non-volatile memory whose readiness signal is active and for which an operation is valid. A suspended operation may be resumed any time after the corresponding readiness signal becomes active and on operation completion the valid bit is set inactive.

Claims12

Dependent claims

A method of operating a non-volatile memory controller comprising a processor and a plurality of non-volatile memory interfaces, the method comprising:

each non-volatile memory interface in the plurality of non-volatile memory interfaces receiving from the processor, multiple non-volatile memory operations to be performed;
wherein each non-volatile memory interface is coupled to a corresponding group of non-volatile memories;
wherein each non-volatile memory operation uniquely identifies a non-volatile memory from within said group of non-volatile memories;
wherein said each non-volatile memory operation comprises a plurality of phases in a predetermined sequence;
a first non-volatile memory interface in the plurality of non-volatile memory interfaces using a first set of bidirectional input-output pins to communicate with a first non-volatile memory in a first group of non-volatile memories to initiate performance of a first phase of a first non-volatile memory operation;
wherein a second phase is specified to be performed subsequent to said first phase, in the first non-volatile memory operation;
the first non-volatile memory interface using said first set of bidirectional input-output pins to further communicate with the first non-volatile memory to initiate performance of a second phase of the first non-volatile memory operation, subsequent to receipt of a first status signal from the first non-volatile memory indicating readiness of the first non-volatile memory;
between performance of said first phase and performance of said second phase, said first non-volatile memory interface using said first set of bidirectional input-output pins to communicate with a second non-volatile memory in said first group of non-volatile memories to initiate performance of another phase of another non-volatile memory operation among said multiple non-volatile memory operations, based at least partially on a second status signal from the second non-volatile memory indicating readiness of the second non-volatile memory and said first status signal from the first non-volatile memory indicating busyness of the first non-volatile memory during performance of the first phase.

5 more elements

A non-volatile memory controller to control transfer of data to and from a plurality of non-volatile memories, the non-volatile memory controller comprising:

a plurality of groups of control ports in one-to-one correspondence with the plurality of non-volatile memories;
wherein a control port in the plurality of groups comprises at least an input pin to independently receive a readiness signal individually from a corresponding non-volatile memory in the plurality of non-volatile memories, said control port further comprising at least an output pin to transmit an enable signal to the corresponding flash memory;
a plurality of storage elements in one-to-one correspondence with the plurality of groups of control ports;
wherein a storage element in the plurality of storage elements stores at least one bit indicative of validity of at least one corresponding operation to be performed on the corresponding non-volatile memory;
a circuit coupled to the plurality of storage elements to receive at least said one bit from each storage element, the circuit being further coupled to the plurality of groups of control ports to receive at least the readiness signal from each control port;
wherein the circuit transmits at least an enable signal to the corresponding non-volatile memory via the output pin in the corresponding control port in response to at least simultaneously (a) said one bit indicative of validity of said at least one corresponding operation being active, and (b) said readiness signal from said corresponding non-volatile memory being active.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/718,944Filed 5 Mar 2010
Published: 8 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/00
Accessing, addressing or allocating within memory systems or architectures
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 3/0679
Single storage device: non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
G06F 3/0688
Plurality of storage devices: non-volatile semiconductor memory arrays