Discrete fourier transform in an integrated circuit device

A method of configuring a programmable integrated circuit device as circuitry for performing a Discrete Fourier Transform operation, said method comprising:

• configuring logic of said programmable integrated circuit device as a floating-point addition stage for adding mantissas of input values of said Discrete Fourier Transform operation;
• and
• configuring logic of said programmable integrated circuit device as a fixed-point stage for multiplying outputs of said floating-point addition stage by twiddle factors, said fixed-point stage comprising:
• memory for storing a plurality of sets of twiddle factors, each of said sets including copies of a respective twiddle factor shifted by different amounts, and
• circuitry for determining a difference between exponents of said outputs of said floating-point stage, and for using said difference as an index to select from among said copies of said respective twiddle factor in each of said sets.

A programmable integrated circuit device comprising:

• logic configurable as a floating-point addition stage for adding mantissas of input values of said Discrete Fourier Transform operation;
• and
• logic configurable as a fixed-point stage for multiplying outputs of said floating-point addition stage by twiddle factors, said fixed-point stage comprising:
• memory for storing a plurality of sets of twiddle factors, each of said sets including copies of a respective twiddle factor shifted by different amounts, and
• circuitry for determining a difference between exponents of said outputs of said floating-point stage, and for using said difference as an index to select from among said copies of said respective twiddle factor in each of said sets.

A machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device as circuitry for performing a Discrete Fourier Transform operation, said instructions comprising:

• instructions to configure logic of said programmable integrated circuit device as a floating-point addition stage for adding mantissas of input values of said Discrete Fourier Transform operation;
• and
• instructions to configure logic of said programmable integrated circuit device as a fixed-point stage for multiplying outputs of said floating-point addition stage by twiddle factors, said fixed-point stage comprising:
• memory for storing a plurality of sets of twiddle factors, each of said sets including copies of a respective twiddle factor shifted by different amounts, and
• circuitry for determining a difference between exponents of said outputs of said floating-point stage, and for using said difference as an index to select from among said copies of said respective twiddle factor in each of said sets.