US 2011/0218792 A1 · Mixed Concurrent And Serial Logic Simulation Of Hardware Designs

Abstract

A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.

Claims50

Dependent claims

A method of simulating a design specified through a hardware description language (HDL), the method comprising:

running an integrated logic simulator, the integrated logic simulator including a serial simulation engine and a concurrent simulation engine;
performing simulation using the serial simulation engine, which performs one simulation at a time;
performing simulation using the concurrent simulation engine, which performs multiple, concurrent simulations;
and
using a computer, synchronizing simulations of the serial simulation engine and the concurrent simulation engine based on classes of events defined by an execution model of the HDL.

2 more elements

Dependencies are inferred from the claim text.

Mixed Concurrent And Serial Logic Simulation Of Hardware Designs

Life of this patent

Mixed Concurrent And Serial Logic Simulation Of Hardware Designs

Life of this patent

Abstract

Claims50