Identification of Critical Enables Using MEA and WAA Metrics
AssigneeAdvanced Micro Devices, Inc.
InventorsVasant Palisetti, Rachida Kebichi, Samuel Naffziger
Life of this patent
Estimating the term…
Abstract
A plurality of sequential nodes in a design file for an electronic device are identified and one or more combinatorial power metric values are computed for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and a power effort measure for at least a first device downstream from the each sequential node at a specified depth. The combinatorial power metric values for the plurality of sequential node are stored and compared to a target power metric value to determine if power consumption at the electronic device meets a predetermined power performance goal.
Claims21
A method comprising:
- identifying one or more sequential nodes in a design file, wherein the design file represents at least a portion of an electronic device, where each sequential node of the design file is an input or output of a respective sequential device or a node that gates a signal provided to a respective sequential device to enable or disable propagation of information through the sequential device;
- determining a combinatorial power metric value for the one or more sequential nodes by computing, for each sequential node, an effective switching capacitance, a switching activity measure, and a power effort measure for all devices downstream from each sequential node up to a specified depth;
- and
- comparing the combinatorial power metric value with a target power metric value to determine if power consumption by the portion of the electronic device meets a predetermined power performance goal.
A system comprising at least one recordable storage medium having stored thereon executable instructions and data which, when executed by at least one processing device, cause the at least one processing device to:
- access a design file representing an electronic device;
- identify each sequential node in the design file that gates a signal provided to a respective sequential device to enable or disable propagation of information through the sequential device;
- calculate a power performance weight at each identified sequential node based upon an effective switching capacitance value, power model information, and switching activity information for the identified sequential node to identify critical enables for the electronic device;
- calculate a normalized sum of all power performance weights for each identified sequential node;
- and
- compare the normalized sum of all power performance weights with a baseline value to evaluate power consumption at the electronic device.
A computer readable storage medium storing instructions operable to control operation of a data processor to:
- access a design file representing an electronic device;
- identify a plurality of sequential nodes for a specified circuit module in the design file where each of the plurality of sequential nodes gates a signal provided to a respective sequential device to enable or disable propagation of information through the sequential device;
- compute and store a combinatorial power metric for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and power effort measure associated with a first test bench power pattern;
- and
- compare the combinatorial power metric with a target power metric value to determine if power consumption at the specified circuit module meets a predetermined power performance goal.
Dependencies are inferred from the claim text.