Method of forming through silicon via with dummy structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hua CHEN, Chen-Shien CHEN, Chen-Cheng KUO, Wen-Wei SHEN
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hua CHEN, Chen-Shien CHEN, Chen-Cheng KUO, Wen-Wei SHEN
Estimating the term…
A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.
A method of forming a through silicon via (TSV) structure, said method comprising:
A method of forming a through silicon via (TSV) structure, said method comprising:
A method of forming a through silicon via (TSV) structure, said method comprising;
Dependencies are inferred from the claim text.
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Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
The interconnections being through-semiconductor vias: comprising use of blind vias during the manufacture
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
Cross-sectional shapes or dispositions: tSVs extending from the semiconductor wafer into back-end-of-line layers
Term end not estimated
The present disclosure relates generally to the field of semiconductor circuits, and more particularly, to a through-silicon-via. (TSV) structure for integrated circuits.
A through-silicon via (TSV) is a vertical electrical connection passing through a silicon wafer or die. TSV technology is important in creating 3-dimensional (3D) packages and 3D integrated circuits. A 3D package, e.g. system in package, chip stack multi-chip module (MCM), etc., contains two or more chips (integrated circuits) stacked vertically so that they occupy less space.
In most 3D packages, the stacked chips arc wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra interposer layer between the chips. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1A-FIG. 1B are a top view and a cross-sectional view of a through silicon via (TSV) structure including one or more dummy structure according to sonic embodiments;
FIG. 2A-FIG. 2C are top views of a through silicon via (TSV) structure including one or more dummy structure according to some embodiments; and
The making and using of various embodiments are discussed in detail below. It should he appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use, and do not limit the scope of the invention.
A structure of through silicon via (TSV) using one or more dummy structure to improve adhesion to the interconnect pad and a method to fabricate the same are provided. FIG. 1A-FIG. 1B are a top view and a cross-sectional view of a through silicon via (TSV) structure including one or more dummy structure according to some embodiments. FIG. 1A shows a top view of the TSV structure 100, including a top pad 102, an interconnect pad 104 and dummy structures 106. The through silicon via structure 100 further includes a vertical conductive post 105 that is connected to the top pad 102. The top pad 102 covers a wider area than the cross section of the vertical conductive post 105. An interconnect pad 104 is located at least partially below the top pad 102. An under layer 107 is also located at least partially below the top pad 102. At least one dummy structure 106 connects the top pad 102 and the under layer 107, fastening the top pad 102 and the interconnect pad 104, The dummy structures 106 are distributed circularly around the vertical conductive post 105 in one embodiment.
FIG. 1B shows a cross section view of the TSV structure 100 along the cross section line 1B according to one embodiment. The top pad 102 is connected to the vertical conductive post 105 to form a TSV. The interconnect pad 104 is also shown under the top pad 102. The dummy structure 106 connects the top pad 102 and the under layer 107 (in FIG. 1A). Depending on implementations, in some embodiments, the under layer 107 can include a seed layer 118, an isolation layer 116, the second passivation layer 114, any other suitable layer (e.g. dummy interconnect layer), or any combinations thereof.