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US 2011/0217840 A1Published application
Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin, Tien-I Bao, Chen-Hua Yu
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Abstract
A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.
Claims20
A method for forming an integrated circuit, the method comprising:
- forming a dielectric layer comprising porogen material;
- removing the porogen material to create pores in the dielectric layer;
- forming a recess in the dielectric layer;
- forming a thin sealant layer in the recess on a sidewall of the dielectric layer;
- and
- forming a conductive material in the recess.
3 more elements
A method for forming an integrated circuit, the method comprising:
- forming a dielectric layer comprising porogen material;
- removing the porogen material to create pores in the dielectric layer by curing the dielectric layer;
- etching an opening in the dielectric layer;
- forming a thin sealant layer in the opening on a sidewall of the dielectric layer by exposing the dielectric layer to an organic gas;
- and
- forming a metal in the opening.
3 more elements
Dependencies are inferred from the claim text.