Dram layout with vertical fets and method of formation
AssigneeMicron Technology, Inc.
InventorTodd R. Abbott
Life of this patent
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Abstract
DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
Claims10
1-96. (canceled)
A method of forming a memory cell comprising the steps of:
- providing a semiconductor substrate;
- providing at least one vertical transistor within the substrate, wherein the at least one vertical transistor has first, second and third doped regions;
- forming a bit line below a surface of the substrate and in connection with the first doped region of the at least one vertical transistor;
- forming a word line on sidewalls of the at least one vertical transistor such that the word line and the bit line form an angle other than about ninety degrees relative to each other;
- providing a capacitive structure in electrical connection with the third doped region of the at least one vertical transistor;
- and
- subjecting the vertical transistor to a salicide process.
Dependencies are inferred from the claim text.