Method of fabricating multi-chip package structure
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorChien-Hao Wang
Life of this patent
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Abstract
A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer or a chip are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures.
Claims20
A method of fabricating a multi-chip package structure, comprising:
- providing a first wafer having an active surface and a back surface opposite to the active surface, a plurality of bonding pads being disposed on the active surface;
- patterning a first insulating layer disposed on the active surface, such that a plurality of openings exposing the bonding pads is formed on the first insulating layer;
- forming a plurality of cavities on a predetermined cutting line of the first wafer by partly removing the first insulating layer, the first wafer, and the first metal layer;
- forming a first circuit layer on the first insulating layer, wherein the first circuit layer has a plurality of first pads;
- providing a second wafer and forming a plurality of conductive bumps on the second wafer;
- electrically connecting the conductive bumps of the second wafer to the first circuit layer;
- forming a second circuit layer having a plurality of second pads on the back surface of the first wafer;
- and
- cutting the first wafer and the second wafer along the predetermined cutting line to form a plurality of separated multi-chip package structures.
A method of fabricating a multi-chip package structure, comprising:
- providing a wafer having an active surface and a back surface opposite to the active surface, a plurality of bonding pads being disposed on the active surface;
- patterning a first insulating layer disposed on the active surface, such that a plurality of openings exposing the bonding pads is formed on the first insulating layer;
- forming a plurality of cavities on a predetermined cutting line of the wafer by partly removing the first insulating layer, the wafer, and the first metal layer;
- forming a first circuit layer on the first insulating layer, wherein the first circuit layer has a plurality of first pads;
- providing at least a chip and forming a plurality of conductive bumps on the chip;
- bonding the conductive bumps of the chip to the first circuit layer;
- forming a second circuit layer having a plurality of second pads on the back surface of the wafer;
- and
- cutting the wafer along the predetermined cutting line to form a plurality of separated multi-chip package structures.
The method of claim 19, wherein the first circuit layer has a plurality of conductive walls electrically connected to a cut cross-section of the first metal layer.
Dependencies are inferred from the claim text.