Variable delay circuit and delay-locked loop including the same
AssigneeKorea University Research and Business Foundation
InventorsChul Woo Kim, Young Ho Kwak
Life of this patent
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Abstract
The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
Claims14
A variable delay circuit comprising:
- a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal;
- a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit;
- a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal;
- and
- a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
A delay-locked loop comprising:
- a variable delay unit that delays an external clock to output an internal clock;
- a replica delay unit that delays the internal clock to generate a feedback clock;
- and
- a phase comparison unit that compares a phase of the feedback clock with a phase of the external clock to generate a delay increase/decrease signal,
- wherein the variable delay unit includes:
- a delay circuit that includes a first delay unit and a second delay unit and delays the external signal to generate the internal signal;
- a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the external signal from the first delay unit and the second delay unit;
- a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal;
- and
- a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
Dependencies are inferred from the claim text.