Architectures and methods for code combiners
AssigneeThe Aerospace Corporation
InventorRajendra Kumar
Life of this patent
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Abstract
Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of −1 and +1 and may comprise an even number of codes. An output of the combining v0,k may be given by: v0=sgn(vi), where vi is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.
Claims20
A method for combining a plurality of codes, the method comprising:
- receiving at a first computer device a plurality of codes, wherein the plurality of codes are binary codes having possible logical values of −1 and +1, wherein the plurality of codes comprise an even number of codes, and wherein the computer device comprises at least one processor and operatively associated memory;
- and
- generating a first output v0,k with the first computer device, wherein the first output v0 at a first time is given by:
- v0=sgn(vi),
- wherein, vi is the sum of the first plurality of codes at the first time.
A system for combining a plurality of codes, the system comprising:
- a first computer device comprising a processor and operatively associated memory, wherein the first computer device is programmed to implement:
- a first combiner module, wherein the first combiner module is configured to generate a first output v0, wherein the first output v0 is given by:
- v0=sgn(vi),
- wherein, vi is the sum of the first plurality of codes at the first time.
The system of 10, wherein a power level of the second plurality of codes is lower than the power level of the first plurality of codes, and wherein the first computer device is further programmed to implement:
- a logic converter configured to receive the first output and generate a logic converter output having a first value when the first output is non-zero and a second value when the first output is zero;
- a logic gate configured to receive the second output and the logic converter output and generate a logic gate output equal to the second output when the first output is equal to 0 and equal to 0 when the first output is non-zero;
- and
- a third combiner configured to receive the first output and the logic gate output and generate a third output equal to the signum of the sum of the first output and the logic gate output.
Dependencies are inferred from the claim text.