Memory power management systems and methods

A method for managing power of a memory array, the method comprising:

• providing an active operating voltage to provide power to the memory array;
• selectably coupling a respective selectably coupleable diode to each of a plurality of memory blocks of the memory array to provide a minimum memory retention voltage to power each of the plurality of memory blocks;
• selectably decoupling a respective selectably coupleable diode from a selected memory block of the memory array to provide an active operating voltage to power the selected memory block;
• and reading from or writing to the selected memory.

An apparatus, comprising:

• circuitry for providing an active operating voltage to provide power to the memory array;
• circuitry for selectably coupling a respective selectably coupleable diode to each of a plurality of memory blocks of the memory array to provide a minimum memory retention voltage to power each of the plurality of memory blocks;
• circuitry for selectably decoupling a respective selectably coupleable diode from a selected memory block of the memory array to provide an active operating voltage to power the selected memory block;
• and
• reading from or writing to the selected memory.