Semiconductor memory device

A semiconductor memory device comprising:

• a first memory cell array region and a second memory cell array region disposed along a first direction;
• a first sense amplifier region interposed between the first and second memory cell array regions, the first sense amplifier region being configured to sense and amplify a signal of a first bit line and a signal of a second bit line, the first bit line extending from the first memory cell array region in the first direction, the second bit line extending from the second memory cell array region in the first direction, wherein a load of the second bit line is larger than a load of the first bit line;
• a second sense amplifier region interposed between the first sense amplifier region and the second memory cell array regions, the second sense amplifier region being configured to sense and amplify a signal of a third bit line and a signal of a fourth bit line, the third bit line extending from the first memory cell array region in the first direction, the fourth bit line extending from the second memory cell array region in the first direction, wherein a load of the fourth bit line is smaller than a load of the third bit line;
• a first column selection transistor connected between the first bit line and a first local data I/O line;
• a second column selection transistor connected between the second bit line and a second local data I/O line;
• a third column selection transistor connected between the third bit line and the first local data I/O line;
• and
• a fourth column selection transistor connected between the fourth bit line and the second local data I/O line,
• wherein a threshold voltage of the first column selection transistor is higher than a threshold voltage of the second column selection transistor, and a threshold voltage of the fourth column selection transistor is higher than a threshold voltage of the third column selection transistor.

A semiconductor memory device comprising:

• a first array of memory cells coupled to a plurality of aligned first sense amplifiers;
• a second array of memory cells coupled to a plurality of aligned second sense amplifiers;
• a first bit line connected to a first memory cell of the first array of memory cells;
• a second bit line connected to a second memory cell of the second array of memory cells;
• a first column select transistor configured to connect to the first bit line and a first local data input/output line in response to a first column select signal;
• and
• a second column select transistor configured to connect to the second bit line and a second local data input/output line in response to a second column select signal,
• wherein a threshold voltage of the first column select transistor is higher than a threshold voltage of the second column select transistor.