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US 2011/0216613 A1Published application
Low power termination for memory modules
AssigneeIntel Corporation
InventorRipan Das
Life of this patent
Estimating the term…
Abstract
An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.
Claims15
An apparatus comprising:
- a memory controller having first circuitry to access a first memory and a second memory of a first memory module coupled to a memory channel, and the memory controller having second circuitry to access a second memory module coupled to the memory channel, the first memory having a first on-die termination (ODT) circuit, and the second memory having a second ODT circuit, and the memory controller having third circuitry to provide a first ODT signal to disable the first ODT circuit of the first memory when the first memory is to be active.
A method comprising:
- determining that a first memory of a first memory module coupled to a memory channel is to be active, the first memory module including the first memory having a first on-die termination (ODT) circuit and a second memory having a second ODT circuit;
- and
- transmitting a first ODT signal to the first memory along the memory channel based on the determining, the first ODT signal to disable the first ODT circuit of the first memory.
Dependencies are inferred from the claim text.