Method and apparatus for calibrating write timing in a memory system

A memory controller to couple to a memory chip that receives a clock signal, the memory controller comprising:

• an interface to output, during a calibration mode, a marking signal and a data-strobe signal to the memory chip, wherein the marking signal identifies a specific clock cycle in the clock signal;
• and
• a feedback input to receive a feedback signal from the memory chip, the feedback signal having been generated at the memory chip by using the marking signal to window the specific clock cycle in the clock signal to generate a windowed clock cycle, and using the data-strobe signal to capture the windowed clock cycle to produce the feedback signal;
• and
• a calibration mechanism which analyzes the feedback signal to calibrate a timing relationship between the data-strobe signal and the clock signal.

A method for calibrating timing relationships between signals involved in performing write operations in a memory system, comprising:

• during a calibration mode, receiving signals from a memory controller at a memory chip in a set of memory chips, wherein the signals include,
• a clock signal which is used as a reference clock by the memory chip,
• a marking signal which includes a pulse that identifies a specific clock cycle in the clock signal, and
• a data-strobe signal that accompanies data signals and is used to strobe the data signals into memory elements at the memory chip;
• and
• facilitating calibration of a timing relationship between the data-strobe signal and the clock signal by,
• the marking signal windowing the specific clock cycle in the clock signal to generate a windowed clock signal,
• the data-strobe signal capturing the windowed clock signal at a phase detector on the memory chip, and
• returning the captured windowed clock signal to the memory controller.

A semiconductor memory device that facilitates calibrating timing relationships between signals involved in performing write operations, the semiconductor memory device comprising:

• a clock input to receive a clock signal;
• a first input to receive a marking signal from a memory controller, wherein the marking signal includes a pulse which identifies a specific clock cycle of the clock signal;
• a second input to receive a data-strobe signal from the memory controller;
• a phase detector that uses the marking signal to window the specific clock cycle of the clock signal, wherein the phase detector uses the data-strobe signal to capture the windowed clock cycle;
• and
• an output which provides the captured windowed clock cycle as a feedback signal to the memory controller.