Semiconductor device and data processor

A semiconductor device comprising:

• a plurality of word lines;
• a plurality of complementary bit lines;
• a plurality of static memory cells disposed correspondingly to the word lines and the complementary bit lines;
• an address decoder that decodes address signals to produce complementary bit line select signals;
• a write circuit that feeds a write signal to each memory cell from a complementary bit line selected by a complementary bit line select signal;
• a plurality of power supply lines that feed a power supply voltage to each group of memory cells which use the complementary bit lines in common;
• a plurality of power switches, each being disposed for each power supply line corresponding to a complementary bit line selected by a complementary bit line select signal for use in common at least, and being so arranged as to be put in an ON state when an unselected level is indicated by the complementary bit line select signal concerned or in an OFF state when a selected level is indicated thereby;
• and
• a plurality of short-circuit switches, each being disposed for providing coupling between an output node of each power switch and an output node of at least one of the other power switches, and being so arranged as to be put in an OFF state in response to a write operation instruction from the write circuit or in an ON state in response to a write non-operation instruction therefrom, where the output nodes of the power switches to be coupled mutually are arranged to correspond to complementary bit lines selected by different complementary bit line select signals at least.

A semiconductor device comprising:

• a plurality of word lines;
• a plurality of complementary bit lines;
• a plurality of static memory cells disposed correspondingly to the word lines and the complementary lines;
• an address decoder that decodes address signals to produce complementary bit line select signals for parallel selection of a plurality of complementary bit lines;
• a write circuit that feeds a write signal to each memory cell from a complementary bit line selected by a complementary bit line select signal, with the exclusion of complementary bit lines that are write-inhibited under the direction of a mask signal;
• a plurality of power supply lines that feed a power supply voltage to each group of memory cells that use the complementary bit lines in common;
• a plurality of power switches, each being disposed for each power supply line corresponding to a complementary bit line selected by a complementary bit line select signal for use in common at least, and being so arranged as to be put in an ON state when an unselected level is indicated by the complementary bit line select signal concerned or in an OFF state when a selected level is indicated thereby;
• a plurality of first short-circuit switches, each being disposed for providing coupling between an output node of each power switch and an output node of at least one of the other power switches, and being so arranged as to be put in an OFF state in response to a write operation instruction from the write circuit or in an ON state in response to a write non-operation instruction therefrom, where the output nodes of the power switches to be coupled mutually are arranged to correspond to complementary bit lines selected by different complementary bit line select signals at least;
• and
• a plurality of second short-circuit switches, each being disposed in parallel with each of the first short-circuit switches, and being so arranged as to be put in an ON state in response to a masking instruction by a corresponding mask bit of the mask signal or in an OFF state in response to an unmasking instruction thereby.

A data processor comprising:

• a CPU that fetches and carries out instructions;
• a first memory block to be accessed by the CPU;
• and
• a data processing unit including a second memory block and being arranged to perform data processing operations under control of the CPU,
• wherein each of the first memory block and the second memory block includes:
• a plurality of word lines disposed row-wise;
• a plurality of complementary bit lines disposed column-wise;
• a plurality of static memory cells disposed correspondingly to the word lines and the complementary bit lines;
• an address decoder that decodes address signals to produce complementary bit line select signals;
• a plurality of power supply lines that feed a power supply voltage to each column of memory cells which use the complementary bit lines in common;
• and
• a power supply circuit that applies a power supply voltage to each column of memory cells through the power supply lines;
• wherein the power supply circuit includes:
• a plurality of power switches, each being disposed for each of the power supply lines;
• and
• a plurality of short-circuit switches, each being so arranged as to provide short-circuiting between output nodes of different power switches;
• and
• wherein, when the complementary bit line select signal concerned indicates an unselected level, the power switch corresponding thereto is put in an ON state so that, in a read operation, a power supply voltage is fed via the short-circuit switch concerned to a selected memory cell column from the power supply line corresponding to a memory cell column being unselected, or in a write operation, a power supply voltage fed via the short-circuit switch concerned to a selected memory cell column is stopped.

A data processor comprising:

• a CPU that fetches and carries out instructions;
• a first memory block to be accessed by the CPU;
• and
• a data processing unit including a second memory block and being arranged to perform data processing operations under control of the CPU;
• wherein each of the first memory block and the second memory block comprises:
• a plurality of word lines;
• a plurality of complementary bit lines;
• a plurality of static memory cells disposed correspondingly to the word lines and the complementary bit lines;
• an address decoder that decodes address signals to produce complementary bit line select signals;
• a write circuit that feeds a write signal to each memory cell from a complementary bit line selected by a complementary bit line select signal;
• a plurality of power supply lines that feed a power supply voltage to each group of memory cells that use the complementary bit lines in common;
• a plurality of power switches, each being disposed for each power supply line corresponding to a complementary bit line selected by a complementary bit line select signal for use in common at least, and being so arranged as to be put in an ON state when an unselected level is indicated by the complementary bit line select signal concerned or in an OFF state when a selected level is indicated thereby;
• and
• a plurality of short-circuit switches, each being disposed for providing coupling between an output node of each power switch and an output node of at least one of the other power switches, and being so arranged as to be put in an OFF state in response to a write operation instruction from the write circuit or in an ON state in response to a write non-operation instruction therefrom, where the output nodes of the power switches to be coupled mutually are arranged to correspond to complementary bit lines selected by different complementary bit line select signals at least.