Techniques for reading from and/or writing to a semiconductor memory device

A method for reading from and writing to a semiconductor memory device comprising:

• arranging a first plurality of memory cells in a matrix of rows and columns in a first memory cell array;
• arranging a second plurality of memory cells in a matrix of row and columns in a second memory cell array;
• coupling the first memory cell array to a first input node of a data sense amplifier latch circuitry via a first bit line input circuitry;
• and
• coupling the second memory cell array to a second input node of the data sense amplifier latch circuitry via a second bit line input circuitry.

An apparatus comprising:

• a first memory cell array comprising a first plurality of memory cells arranged in a matrix of rows and columns;
• a second memory cell array comprising a second plurality of memory cells arranged in a matrix of row and columns;
• a data sense amplifier latch circuitry comprising a first input node and a second input node;
• a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry via a bit line;
• and
• a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry via the bit line.

A method for reading from and writing to a semiconductor memory device comprising:

• arranging a first plurality of memory cells in a matrix of rows and columns in a first memory cell array;
• arranging a second plurality of memory cells in a matrix of row and columns in a second memory cell array;
• coupling the first memory cell array to a first input node of a data sense amplifier latch circuitry via a bit line;
• and
• coupling the second memory cell array to a second input node of the data sense amplifier latch circuitry via the bit line.