Data output circuit of semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorsKwang-Hyun KIM, Kang-Youl Lee
Life of this patent
Estimating the term…
Abstract
A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.
Claims25
A data output circuit of a semiconductor memory device, comprising:
- a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data;
- and
- an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group,
- wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.
A data output circuit of a semiconductor memory device, comprising:
- a pipe latch unit configured to store input parallel data, and align even data of the stored data in response to a plurality of even alignment control signals to output a first output data, and align odd data of the stored data in response to a plurality of odd alignment control signals to output a second output data;
- and
- an alignment control signal generating unit configured to generate the plurality of even and odd alignment control signals in response to a burst-type information and a seed address group,
- wherein the alignment control signal generating unit outputs the even alignment control signals as the odd alignment control signals in a normal mode, and outputs the odd alignment control signals by swapping even alignment control signals in a swap mode.
A data output circuit of a semiconductor memory device, comprising:
- a pipe latch output control unit configured to generate a pipe latch output control signal in response to a read column access strobe (CAS) signal, which is set by a read command;
- an alignment control signal generating unit configured to generate a plurality of alignment control signals for swapping data in a swap mode detected in response to a burst-type information and a seed address group;
- a pipe latch unit configured to store input parallel data and align the stored data in response to the plurality of alignment control signals to output serial output data;
- and
- a data driving unit configured to output the serial output data of the pipe latch unit in synchronism with a clock signal.
Dependencies are inferred from the claim text.