Method for operating semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsYoshimasa Mikajiri, Shigeto Oota, Masaru Kito, Ryouhei Kirisawa
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Abstract
According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential.
Claims18
A method for operating a semiconductor memory device, the semiconductor memory device including:
- a substrate;
- a stacked body including a plurality of word electrode layers and a plurality of insulating layers alternately stacked on the substrate;
- a memory film including a charge storage film provided on an inner wall of a memory hole punched through the stacked body;
- a channel body provided inside the memory film in the memory hole;
- a select transistor including a select gate stacked on the stacked body and connected to an end portion of the channel body;
- and
- a wiring connected to the select transistor,
- the method comprising:
- boosting a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer;
- and
- after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, decreasing a potential of the word electrode layer to a second erase potential lower than the first erase potential.
A method for operating a semiconductor memory device, the semiconductor memory device including:
- a substrate;
- a stacked body including a plurality of word electrode layers and a plurality of insulating layers alternately stacked on the substrate;
- a memory film including a charge storage film provided on an inner wall of a memory hole punched through the stacked body;
- a channel body provided inside the memory film in the memory hole;
- a select transistor including a select gate stacked on the stacked body and connected to an end portion of the channel body;
- and
- a wiring connected to the select transistor,
- the method comprising:
- boosting a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer;
- and
- after the boosting of the potential of the channel body, with the wiring maintained at the first erase potential, decreasing a potential of the word electrode layer to a second erase potential lower than the first erase potential, and setting a potential of the select gate to a third erase potential lower than the first erase potential and higher than the second erase potential.
A method for operating a semiconductor memory device, the semiconductor memory device including:
- a substrate;
- a stacked body including a plurality of word electrode layers and a plurality of insulating layers alternately stacked on the substrate;
- a memory film including a charge storage film provided on an inner wall of a memory hole punched through the stacked body;
- a channel body provided inside the memory film in the memory hole;
- a select transistor including a select gate stacked on the stacked body and connected to an end portion of the channel body;
- and
- a wiring connected to the select transistor,
- the method comprising:
- boosting a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer;
- and
- after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, setting a potential of the word electrode layer to a potential lower than the first erase potential and setting a potential of a relatively upper word electrode layer of the word electrode layers is made lower than a potential of a lower word electrode layer of the word electrode layers.
Dependencies are inferred from the claim text.