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US 2011/0216593 A1Published application
Nand flash memory
AssigneeKabushiki Kaisha Toshiba
InventorsKIYOFUMI SAKURAI, Takuya Futatsuyama
Life of this patent
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Abstract
A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.
Claims21
(canceled)
A NAND flash memory comprising:
- a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction;
- first and second transfer transistor blocks disposed in order in the first direction at one end in a second direction intersecting with the first direction of the memory cell array;
- word lines disposed in the first NAND block and connected to the first transfer transistor block;
- and
- word lines disposed in the third NAND block and connected to the second transfer transistor block by replacing a physical position of the word lines to a reversal state.
2 more elements
A NAND flash memory comprising:
- a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction;
- first and second transfer transistor blocks disposed in order in the first direction at one end in a second direction intersecting with the first direction of the memory cell array;
- word lines disposed in the first NAND block and connected to the first transfer transistor block;
- and
- word lines disposed in the third NAND block and connected to the second transfer transistor block,
- wherein the word lines in the first NAND block are comprised of n word lines, n being an even number, in which the ends on the first transfer transistor block side are bended, and n+2 word lines in which the ends on the first transfer transistor block side are bended in the opposite direction to the direction in which the n word lines are bended.
3 more elements
A NAND flash memory comprising:
- a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction;
- first and second transfer transistor blocks disposed in order in the first direction at one end in a second direction intersecting with the first direction of the memory cell array;
- word lines disposed in the first NAND block and connected to the first transfer transistor block;
- word lines disposed in the third NAND block and connected to the second transfer transistor block,
- a drain contact portion disposed between the first and second NAND blocks;
- and
- a source contact portion disposed between the second and third NAND blocks,
- wherein a width in the first direction of the drain contact portion is larger than a width in the first direction of the source contact portion.
5 more elements
Dependencies are inferred from the claim text.