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US 2011/0216579 A1Published application
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsMASANAO YAMAOKA, KOICHIRO ISHIBASHI, SHIGEZUMI MATSUI, KENICHI OSADA
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Abstract
A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
Claims4
1-15. (canceled)
A semiconductor device comprising:
- a logic circuit including a plurality of MOS transistors and a source node;
- a SRAM memory cell array including a plurality of memory cell transistors;
- a low voltage supply line to supply a low voltage;
- a switch coupled between the low voltage supply line and the source node;
- and
- a voltage control circuit to control a substrate bias of the memory cell array,
- wherein the memory transistors includes nMOS transistors, and in a standby mode, the switch is off and a threshold voltage of the nMOS transistors is higher than the threshold voltage of the nMOS transistors in an operation mode.
4 more elements
Dependencies are inferred from the claim text.