Variable resistance nonvolatile storage device

A variable resistance nonvolatile storage device, comprising:

• a memory cell array including memory cells arranged in a matrix, each of said memory cells including a variable resistance element and a first switch element connected in series with said variable resistance element, said variable resistance element including (i) a first electrode, (ii) a second electrode, and (iii) a nonvolatile variable resistance layer disposed between said first electrode and said second electrode, said nonvolatile variable resistance layer having a resistance state that reversibly changes between a high resistance state and a low resistance state according to a polarity of a voltage to be applied between said first electrode and said second electrode;
• a selection circuit that selects at least one of said memory cells from said memory cell array;
• a high-resistance-state write circuit that applies a voltage to said memory cell selected by said selection circuit so as to change a resistance state of said variable resistance element included in said selected memory cell, from the low resistance state to the high resistance state by applying a positive voltage to said second electrode of said variable resistance element with respect to said first electrode of said variable resistance element;
• and
• a low-resistance-state write circuit that applies a voltage to said memory cell selected by said selection circuit so as to change the resistance state of said variable resistance element from the high resistance state to the low resistance state by applying a positive voltage to said first electrode with respect to said second electrode,
• wherein said low-resistance-state write circuit includes a first driving circuit and a second driving circuit both of which apply the voltage to said memory cell, said first driving circuit having an output terminal connected to an output terminal of said second driving circuit,
• said first driving circuit supplies a first current when said low-resistance-state write circuit applies the voltage to said memory cell, and
• said second driving circuit (i) supplies a second current when a voltage at the output terminal of said first driving circuit is higher than a predetermined first reference voltage, and (ii) is in a high impedance state when the voltage at the output terminal of said first driving circuit is lower than the first reference voltage, in the case where said low-resistance-state write circuit applies the voltage to said memory cell.