US 2011/0216571 A1 · SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE

Abstract

A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. In order to reduce the number of wirings, a writing word line to which the gate of the writing transistor is not connected is substituted for the reading word line. Further, the writing bit line is substituted for the reading bit line.

Claims21

Dependent claims

A semiconductor memory device comprising:

a first memory cell including a first transistor, a second transistor, and a capacitor;
a second memory cell including a third transistor;
a first line;
a second line;
a third line;
a fourth line;
and
a fifth line,
wherein a gate of the first transistor is electrically connected to the first line,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor,
wherein a second electrode of the capacitor and a gate of the third transistor are electrically connected to the second line,
wherein the other of the source and the drain of the first transistor is electrically connected to the third line,
wherein one of a source and a drain of the second transistor is electrically connected to the fourth line, and
wherein the other of the source and the drain of the second transistor is electrically connected to the fifth line.

11 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and semiconductor device

Life of this patent

Semiconductor memory device and semiconductor device

Life of this patent

Abstract

Claims21