US 2011/0216569 A1 · CONTENT ADDRESSABLE MEMORY DEVICE

Abstract

A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.

Claims35

Dependent claims

A content addressable memory device comprising:

a first memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of first match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the first memory array;
a plurality of first determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the first memory array, according to a voltage of the first match line;
a second memory array comprising a plurality of content addressable memory cells arranged in a matrix,
a plurality of second match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the second memory array;
a plurality of second determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the second memory array, according to a voltage of the second match line;
and
a control circuit operable to direct to start searching in the second memory array after two or more cycles after searching has been started in the first memory array, and operable to direct to stop searching in the second memory array according to a voltage of the first match line after the searching in the first memory array.

5 more elements

A content addressable memory device, comprising:

a first memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of first match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the first memory array;
a plurality of first determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the first memory array, according to a voltage of the first match line;
a second memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of second match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the second memory array;
a plurality of second determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the second memory array, according to a voltage of the second match line;
a third memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of third match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the third memory array;
a plurality of third determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the third memory array, according to a voltage of the third match line;
a fourth memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of fourth match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the fourth memory array;
a plurality of fourth determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the fourth memory array, according to a voltage of the fourth match line;
and
a control circuit operable to direct to start searching in the second memory array, the third memory array, and the fourth array after two or more cycles after searching has been started in the first memory array, and operable to direct to stop searching in the second memory array, the third memory array, and the fourth memory array, according to a voltage of the first match line after the searching in the first memory array.

11 more elements

A content addressable memory device, comprising:

a first memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of first match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the first memory array;
a plurality of first determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the first memory array, according to a voltage of the first match line;
a second memory array comprising a plurality of content addressable memory cells arranged in a matrix,
a plurality of second match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the second memory array;
a plurality of second determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the second memory array, according to a voltage of the second match line;
a third memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of third match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the third memory array;
a plurality of third determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the third memory array, according to a voltage of the third match line;
a fourth memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of fourth match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the fourth memory array;
a plurality of fourth determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the fourth memory array, according to a voltage of the fourth match line;
and
a control circuit operable to direct to start searching in the third memory array and the fourth array after two or more cycles after searching has been started in the second memory array, and operable to direct to stop searching in the third memory array and the fourth memory array, according to a voltage of the second match line after the searching in the second memory array.

11 more elements

A content addressable memory device, comprising:

a first memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of first match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the first memory array;
a plurality of first determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the first memory array, according to a voltage of the first match line;
a second memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of second match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the second memory array;
a plurality of second determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the second memory array, according to a voltage of the second match line;
a third memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of third match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the third memory array;
a plurality of third determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the third memory array, according to a voltage of the third match line;
a fourth memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of fourth match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the fourth memory array;
a plurality of fourth determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the fourth memory array, according to a voltage of the fourth match line;
and
a control circuit operable to direct to start searching in the second memory array after two or more cycles after searching in the first memory array has been started, operable to direct to stop searching in the second memory array, according to a voltage of the first match line after the searching in the first memory array, operable to direct to start searching in the third memory array and the fourth memory array after two or more cycles after searching has been started in the second memory array, and operable to direct to stop searching in the third memory array and the fourth memory array, according to a voltage of the first match line after searching in the first memory array, and to a voltage of the second match line after searching in the second memory array.

11 more elements

A content addressable memory device, comprising:

a first memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of first match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the first memory array;
a plurality of first determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the first memory array, according to a voltage of the first match line;
a second memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of second match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the second memory array;
a plurality of second determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the second memory array, according to a voltage of the second match line;
a third memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of third match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the third memory array;
a plurality of third determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the third memory array, according to a voltage of the third match line;
a fourth memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a plurality of fourth match lines each coupled to each of a plurality of content addressable memory cells belonging to corresponding entry in the fourth memory array;
a plurality of fourth determination circuits each operable to determine coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of the fourth memory array, according to a voltage of the fourth match line;
and
a control circuit operable to direct to start searching in the first memory array and the third memory array concurrently, operable to direct to start searching in the second memory array and the fourth memory array after two or more cycles after searching has been started in the first memory array and the third memory array, and operable to direct to stop searching in the second memory array and the fourth memory array, according to a voltage of the first match line after searching in the first memory array, and to a voltage of the third match line after searching in the third memory array.

11 more elements

A content addressable memory device comprising:

a first memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a second memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a first match line coupled to a plurality of content addressable memory cells of one row in the first memory array;
and
a second match line coupled to a plurality of content addressable memory cells of one row in the second memory array,
wherein the first memory array comprises a search transistor operable to discharge the first match line coupled to the content addressable memory cell, when data in the content addressable memory cell and search data is of non-coincidence,
wherein the second memory array comprises a search transistor operable to discharge the second match line coupled to the content addressable memory cell, when data in the content addressable memory cell and search data is of non-coincidence, and
wherein the content addressable memory device further comprises a transfer circuit operable to separate the first match line and the second match line in a period of searching the first memory array and the second memory array, and operable to transmit voltage of the first match line to the second match line.

5 more elements

A content addressable memory device comprising:

a first memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a second memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a first match line coupled to a plurality of content addressable memory cells of one row in the first memory array;
a second match line coupled to a plurality of content addressable memory cells of one row in the second memory array,
a first pre-charge circuit coupled to either the first match line and the second match line;
and a first transfer circuit operable to couple the first match line and the second match line in a period other than a period of searching the first memory array and the second memory array, operable to separate the first match line and the second match line in a period of searching the first memory array and the second memory array, and operable to transmit voltage of the first match line to the second match line,
wherein the first memory array comprises a search transistor operable to discharge the first match line coupled to the content addressable memory cell, when data in the content addressable memory cell and search data is of non-coincidence,
wherein the second memory array comprises a search transistor operable to discharge the second match line coupled to the content addressable memory cell, when data in the content addressable memory cell and search data is of non-coincidence, and
wherein the first pre-charge circuit pre-charges the first match line and the second match line in a prescribed period other than a period of searching the first memory array and the second memory array,
wherein the content addressable memory device further comprises:
a third memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a fourth memory array comprising a plurality of content addressable memory cells arranged in a matrix;
a third match line coupled to a content addressable memory cell of one row in the third memory array;
a fourth match line coupled to a content addressable memory cell of one row in the fourth memory array;
a second pre-charge circuit coupled to either the third match line and the fourth match line;
a discharging circuit coupled to the fourth match line;
and
a second transfer circuit operable to couple the third match line and the fourth match line in a period other than a period of searching the third memory array and the fourth memory array, operable to separate the third match line and the fourth match line in a period of searching the third memory array and the fourth memory array, and operable to transmit voltage of the third match line to the fourth match line,
wherein the third memory array comprises a search transistor operable to discharge the third match line coupled to the content addressable memory cell, when data in the content addressable memory cell and search data is of non-coincidence,
wherein the fourth memory array comprises a search transistor operable to discharge the fourth match line coupled to the content addressable memory cell, when data in the content addressable memory cell and search data is of non-coincidence, and
wherein the second pre-charge circuit pre-charges the third match line and the fourth match line, when voltage of the second match line is not discharged, in a prescribed period other than a period of searching the third memory array and the fourth memory array.

18 more elements

Dependencies are inferred from the claim text.

Content addressable memory device

Life of this patent

Content addressable memory device

Life of this patent

Abstract

Claims35