System interconnection inverter

Abstract

The present invention includes: an inverter 1 configured to perform pulse wide modulation on an output from a DC power source 5; a first capacitor pair 41 provided at an input side of the inverter and including two capacitors serially connected to form a neutral point; a second capacitor pair 42 provided at an output side of the inverter and including two capacitors serially connected to form a neutral point; a bypass path g for a leakage current formed by connecting the neutral point of the first capacitor pair and the neutral point of the second capacitor pair to each other; at least one common mode choke coil 3 provided between the first capacitor pair and the second capacitor pair and configured to suppress a common mode current generated in the inverter; and an output filter 2 configured to convert a voltage, which is outputted from the inverter and subjected to the pulse wide modulation, into a voltage in a sine wave form.

Dependencies are inferred from the claim text.