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US 2011/0216258 A1Published application
Differential amplifier circuit, display panel driver, and display device
AssigneeRenesas Electronics Corporation
InventorFumihiko KATO
Life of this patent
Estimating the term…
Abstract
A differential amplifying circuit includes first and second differential transistor pairs, first and second constant current sources, first and second current mirror circuits and first and second output transistors. The differential amplifying circuit also includes a feedback circuit configured to perform feed-back operations to the first and second current mirror circuits to restrain reduction of gate voltages of the output transistors. The constant current sources are configured to increase bias currents in response to reduction of the gate voltages of the output transistors.
Claims10
A differential amplifying circuit comprising:
- a first differential transistor pair of PMOS transistors that have gates connected with a non-inversion input and an inversion input, respectively;
- a first constant current source section configured to supply a first bias current to said first differential transistor pair;
- a second differential transistor pair of NMOS transistors that have gates connected with said non-inversion input and said inversion input, respectively;
- a second constant current source section configured to supply a second bias current to said second differential transistor pair;
- a first current mirror circuit connected with said first differential transistor pair;
- a second current mirror circuit connected with said second differential transistor pair;
- a PMOS output transistor connected between a positive power supply line and an output terminal and having a gate connected with an output of said second current mirror circuit;
- an NMOS output transistor connected between a negative power supply line and said output terminal and having a gate connected with an output of said first current mirror circuit;
- and
- a feedback circuit configured to perform a feed-back operation to said first current mirror circuit to restrain reduction of the gate voltage of said NMOS output transistor, and perform a feed-back operation to said second current mirror circuit to restrain increase of the gate voltage of said PMOS output transistor,
- wherein said first constant current source section is configured to increase said first bias current in response to reduction of a gate voltage of said PMOS output transistor, and said second constant current source section is configured to increase said second bias current in response to increase of a gate voltage of said NMOS output transistor.
8 more elements
A display panel driver which drives a display panel, comprising:
- an output circuit which comprises a differential amplifying circuit,
- wherein said differential amplifying circuit comprises:
- a first differential transistor pair of PMOS transistors that have gates connected with a non-inversion input and an inversion input, respectively;
- a first constant current source section configured to supply a first bias current to said first differential transistor pair;
- a second differential transistor pair of NMOS transistors that have gates connected with said non-inversion input and said inversion input, respectively;
- a second constant current source section configured to supply a second bias current to said second differential transistor pair;
- a first current mirror circuit connected with said first differential transistor pair;
- a second current mirror circuit connected with said second differential transistor pair;
- a PMOS output transistor connected between a positive power supply line and an output terminal and having a gate connected with an output of said second current mirror circuit;
- an NMOS output transistor connected between a negative power supply line and said output terminal and having a gate connected with an output of said first current mirror circuit;
- and
- a feedback circuit configured to perform a feed-back operation to said first current mirror circuit to restrain reduction of the gate voltage of said NMOS output transistor, and perform a feed-back operation to said second current mirror circuit to restrain increase of the gate voltage of said PMOS output transistor, and
- wherein said first constant current source section is configured to increase said first bias current in response to reduction of a gate voltage of said PMOS output transistor, and said second constant current source section is configured to increase said second bias current in response to increase of a gate voltage of said NMOS output transistor.
10 more elements
A display apparatus comprising:
- a display panel;
- and
- a diver comprising an output circuit configured to drive a data line of said display panel,
- wherein said output circuit comprises a differential amplifying circuit which comprises:
- a first differential transistor pair of PMOS transistors that have gates connected with a non-inversion input and an inversion input, respectively;
- a first constant current source section configured to supply a first bias current to said first differential transistor pair;
- a second differential transistor pair of NMOS transistors that have gates connected with said non-inversion input and said inversion input, respectively;
- a second constant current source section configured to supply a second bias current to said second differential transistor pair;
- a first current mirror circuit connected with said first differential transistor pair;
- a second current mirror circuit connected with said second differential transistor pair;
- a PMOS output transistor connected between a positive power supply line and an output terminal and having a gate connected with an output of said second current mirror circuit;
- an NMOS output transistor connected between a negative power supply line and said output terminal and having a gate connected with an output of said first current mirror circuit;
- and
- a feedback circuit configured to perform a feed-back operation to said first current mirror circuit to restrain reduction of the gate voltage of said NMOS output transistor, and perform a feed-back operation to said second current mirror circuit to restrain increase of the gate voltage of said PMOS output transistor, and
- wherein said first constant current source section is configured to increase said first bias current in response to reduction of a gate voltage of said PMOS output transistor, and said second constant current source section is configured to increase said second bias current in response to increase of a gate voltage of said NMOS output transistor.
12 more elements
Dependencies are inferred from the claim text.