Timing Controller and Clock Signal Detection Circuit Thereof

A timing controller for generating pixel data in a display driving system, comprising:

• a delay locked loop for delaying an input clock signal to generate a feedback clock signal;
• and
• is a clock signal detection circuit for detecting the input clock signal and the feedback clock signal, the clock signal detection circuit comprising:
• a lock detection circuit for detecting whether the input clock signal and the feedback clock signal of the delay locked loop are in phase;
• a duty cycle detection circuit for detecting whether the duty cycle of the input clock signal is within a percentage range;
• a first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, for outputting a detecting result signal which is at a first logic level when the input clock signal are in phase with the feedback clock signal, and when the duty cycle of the input clock signal is within a percentage range;
• and
• a counter for outputting a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.