Phase-locked loop circuit, semiconductor integrated circuit, electronic device, and control method of phase-locked loop circuit

A phase-locked loop circuit comprising:

• a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison;
• an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to said error signal;
• a frequency dividing section configured to generate said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio;
• an oscillator control section configured to generate an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating section on a basis of said error signal;
• and
• a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of said frequency dividing section on a basis of said error signal;
• wherein said oscillator control section and said frequency divider control section are configured such that said oscillating section and said frequency dividing section perform interlocked operation on a basis of said error signal both in a pull-in process and at a time of locking.

A semiconductor integrated circuit comprising:

• a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison, an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to said error signal, a frequency dividing section configured to generate said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio, an oscillator control section configured to generate an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating section on a basis of said error signal, and a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of said frequency dividing section on a basis of said error signal;
• and
• a signal processing section configured to operate on a basis of said internal clock signal;
• wherein said oscillator control section and said frequency divider control section are configured such that said oscillation control signal and said frequency division control signal respond having a predetermined relation to each other on a basis of said error signal both in a pull-in process and at a time of locking, or
• said oscillator control section and said frequency divider control section are configured such that said oscillating section and said frequency dividing section perform interlocked operation on a basis of said error signal both in a pull-in process and at a time of locking.

An electronic device comprising:

• a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison, an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to said error signal, a frequency dividing section configured to generate said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio, an oscillator control section configured to generate an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating section on a basis of said error signal, and a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of said frequency dividing section on a basis of said error signal;
• and
• a signal processing section configured to operate on a basis of said internal clock signal;
• wherein said oscillator control section and said frequency divider control section are configured such that said oscillation control signal and said frequency division control signal respond having a predetermined relation to each other on a basis of said error signal both in a pull-in process and at a time of locking, or
• said oscillator control section and said frequency divider control section are configured such that said oscillating section and said frequency dividing section perform interlocked operation on a basis of said error signal both in a pull-in process and at a time of locking.

A control method of a phase-locked loop circuit, said control method comprising the steps of:

• comparing a phase of an external reference clock signal with a phase of a comparison clock signal, and generating an error signal corresponding to a result of comparison;
• generating an internal clock signal of an oscillation frequency corresponding to said error signal;
• generating said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio;
• generating an oscillation control signal for controlling frequency of said internal clock signal on a basis of said error signal;
• and
• generating a frequency division control signal for controlling a bias current of a circuit performing said frequency dividing on a basis of said error signal;
• wherein said oscillation control signal and said frequency division control signal are made to respond having a predetermined relation to each other on a basis of said error signal both in a pull-in process and at a time of locking.

A control method of a phase-locked loop circuit, said control method comprising the steps of:

• comparing a phase of an external reference clock signal with a phase of a comparison clock signal, and generating an error signal corresponding to a result of comparison;
• generating an internal clock signal of an oscillation frequency corresponding to said error signal;
• generating said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio;
• generating an oscillation control signal for controlling frequency of said internal clock signal on a basis of said error signal;
• and
• generating a frequency division control signal for controlling a bias current of a circuit performing said frequency dividing on a basis of said error signal;
• wherein the step of generating said internal clock signal and the step of generating said comparison clock signal are operated so as to be interlocked with each other on a basis of said error signal both in a pull-in process and at a time of locking.

A phase-locked loop circuit comprising:

• phase and frequency comparing means for comparing a phase of an external reference clock signal with a phase of a comparison clock signal, and generating an error signal corresponding to a result of comparison;
• oscillating means for generating an internal clock signal of an oscillation frequency corresponding to said error signal;
• frequency dividing means for generating said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio;
• oscillator control means for generating an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating means on a basis of said error signal;
• and
• frequency divider control means for generating a frequency division control signal for controlling a bias current of said frequency dividing means on a basis of said error signal;
• wherein said oscillator control means and said frequency divider control means are configured such that said oscillation control signal and said frequency division control signal respond having a predetermined relation to each other on a basis of said error signal both in a pull-in process and at a time of locking.

A phase-locked loop circuit comprising:

• phase and frequency comparing means for comparing a phase of an external reference clock signal with a phase of a comparison clock signal, and generating an error signal corresponding to a result of comparison;
• oscillating means for generating an internal clock signal of an oscillation frequency corresponding to said error signal;
• frequency dividing means for generating said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio;
• oscillator control means for generating an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating means on a basis of said error signal;
• and
• frequency divider control means for generating a frequency division control signal for controlling a bias current of said frequency dividing means on a basis of said error signal;
• wherein said oscillator control means and said frequency divider control means are configured such that said oscillating means and said frequency dividing means perform interlocked operation on a basis of said error signal both in a pull-in process and at a time of locking.

A semiconductor integrated circuit comprising:

• phase and frequency comparing means for comparing a phase of an external reference clock signal with a phase of a comparison clock signal, and generating an error signal corresponding to a result of comparison, oscillating means for generating an internal clock signal of an oscillation frequency corresponding to said error signal, frequency dividing means for generating said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio, oscillator control means for generating an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating means on a basis of said error signal, and frequency divider control means for generating a frequency division control signal for controlling a bias current of said frequency dividing means on a basis of said error signal;
• and
• signal processing means for operating on a basis of said internal clock signal;
• wherein said oscillator control means and said frequency divider control means are configured such that said oscillation control signal and said frequency division control signal respond having a predetermined relation to each other on a basis of said error signal both in a pull-in process and at a time of locking, or
• said oscillator control means and said frequency divider control means are configured such that said oscillating means and said frequency dividing means perform interlocked operation on a basis of said error signal both in a pull-in process and at a time of locking.

An electronic device comprising:

• phase and frequency comparing means for comparing a phase of an external reference clock signal with a phase of a comparison clock signal, and generating an error signal corresponding to a result of comparison, oscillating means for generating an internal clock signal of an oscillation frequency corresponding to said error signal, frequency dividing means for generating said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio, oscillator control means for generating an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating means on a basis of said error signal, and frequency divider control means for generating a frequency division control signal for controlling a bias current of said frequency dividing means on a basis of said error signal;
• and
• signal processing means for operating on a basis of said internal clock signal;
• wherein said oscillator control means and said frequency divider control means are configured such that said oscillation control signal and said frequency division control signal respond having a predetermined relation to each other on a basis of said error signal both in a pull-in process and at a time of locking, or
• said oscillator control means and said frequency divider control means are configured such that said oscillating means and said frequency dividing means perform interlocked operation on a basis of said error signal both in a pull-in process and at a time of locking.