Novel switched phase and frequency detector based dpll circuit with excellent wander and jitter performance and fast frequency acquisition

A method comprising:

• receiving a reference clock timing signal and a VCXO clock timing signal at a re-sampled NCO phase detector;
• determining a phase output;
• receiving the phase output and the VCXO clock timing signal at a resampler;
• resampling the phase output;
• receiving the resampled phase output at a subtractor;
• subtracting the resampled phase output from a calculated mean value of the phase output;
• receiving the reference clock timing signal and the VCXO clock timing signal at a frequency detector;
• and
• switching between the re-sampled NCO phase detector and the frequency detector as the active detector dependent upon a frequency lock status.

A system comprising:

• a frequency detector providing enable output;
• an accumulator in communication with a reference clock driven by the enable output;
• a resampler for resampling the accumulator output by a VCXO clock;
• a calculator for calculating a detection voltage and a frequency error from the resampler output;
• and
• a lock indicator wherein the lock indicator setting is determined by the detection voltage.