Dc offset canceller, receiving apparatus and dc offset cancellation method

A receiving apparatus comprising:

• a low noise amplifier configured to amplify a radio signal received by an antenna to output an output signal;
• an oscillator configured to generate a local signal;
• a mixer configured to multiply the output signal of the low noise amplifier and the local signal to perform frequency conversion to generate an analog signal;
• a low pass filter configured to remove a high frequency component from the analog signal;
• a first DA converter configured to DA-convert first correction data into a first correction voltage;
• a first adder configured to add an output signal of the low pass filter and the first correction voltage to output a first added signal;
• an amplifier configured to amplify the first added signal to output an amplified signal;
• a comparator configured to compare the amplified signal and a reference voltage to output a comparison result;
• an averaging circuit configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results, in a predetermined time period;
• a successive approximation register configured to sequentially set each bit of the first correction data based on the majority decision result so that a DC offset in the amplified signal decreases;
• an AD converter configured to AD-convert the amplified signal to output AD-converted data;
• and
• a demodulator configured to demodulate the AD-converted data.

A DC offset cancellation method comprising:

• DA-converting first correction data into a first correction voltage by a first DA converter;
• adding an input signal and the first correction voltage to output a first added signal by a first adder;
• amplifying the first added signal to output an amplified signal by an amplifier;
• comparing the amplified signal and a reference voltage to output a comparison result by a comparator;
• receiving the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period, by an averaging circuit;
• and
• sequentially setting each bit of the first correction data based on the majority decision result so that a DC offset in the amplified signal decreases, by a successive approximation register.