High speed latch circuit with metastability trap and filter

A method of synchronizing an input signal, the method comprising:

• sampling the input signal at both a first edge and a second edge of a common clocking signal, said second edge opposing said first edge;
• confirming that said sampled input signal is of a consistent value for two consecutive opposing edges of the common clocking signal;
• and
• outputting a signal responsive to a previous synchronized output value and said confirmed sampled input signal.

A synchronizer comprising:

• a first set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of said first set responsive to a first edge of a common clocking signal and the penultimate latch of said first set responsive to a second edge of the common clocking signal, the second edge opposing the first edge;
• a second set of three serially coupled latches coupled to the common clocking signal, the first and the ultimate latch of said second set responsive to the second edge of the common clocking signal and the penultimate latch of said second set responsive to the first edge of the common clocking signal;
• a means for receiving a signal to be synchronized, said means for receiving coupled to the input of the first latch of said first set and to the input of the first latch of said second set;
• and
• a filter arranged to pass the output of each of said first set and said second set responsive to the penultimate latch of the set exhibiting a consonant output for two consecutive opposing edges of the common clocking signal.