Method for tracking delay locked loop clock
AssigneeElite Semiconductor Memory Technology Inc.
InventorChung-Zen Chen
Life of this patent
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Abstract
A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.
Claims18
A method for tracking a delay locked loop (DLL) clock and adapted to a DDL, comprising:
- allowing an external clock signal to pass through delay cells of the DLL during a first period of the external clock signal when a first transition edge of a track signal applied on the DLL occurs;
- inhibiting the external clock signal to pass through the delay cells of the DLL and counting the number of the delay cells through which the external clock signal pass during the first period of the external clock signal when a first transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the clock external signal;
- and
- resetting a delay time of each of the delay cells such that a ratio of the delay time to the first period of the external clock signal is kept within a range when a reset signal is asserted, wherein whether the reset signal is asserted is triggered by the first transition edge of the sensing signal and the range is from 10% to 15%.
A method for tracking a delay locked loop (DLL) clock and adapted to a DDL, comprising:
- allowing an external clock signal to pass through delay cells of the DLL during a first period of the external clock signal when a first transition edge of a track signal applied on the DLL occurs;
- inhibiting the external clock signal to pass through the delay cells of the DLL when a first transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the clock external signal and a xth delay cell of the delay cells is remained at a first state during the first period of the external clock signal, wherein x is an integer larger than 5;
- and
- resetting a delay time of each of the delay cells such that a ratio of the delay time to the first period of the external clock signal is kept within a range when a reset signal is asserted, wherein whether the reset signal is asserted is triggered by the first transition edge of the sensing signal and the state of the xth delay cell during the first period of the external clock signal, and the range is from 10% to 15%.
Dependencies are inferred from the claim text.