US 2011/0215846 A1Published application

Phase locked loop circuit and control method thereof

AssigneeRenesas Electronics Corporation

InventorManabu FURUTA

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Abstract

A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock.

Claims13

Dependent claims

A phase locked loop circuit comprising:

a selector that selects one of a plurality of clocks as an input clock;
a first frequency divider that divides a frequency of the input clock;
a second frequency divider that divides a frequency of a feedback clock;
a phase difference detector that detects a phase difference between the clock divided by the first frequency divider and the clock divided by the second frequency divider;
a first voltage controlled oscillator that comprises a first voltage holding circuit holding an input voltage according to the phase difference, the first voltage controlled oscillator generating a first intermediate clock based on the input voltage according to the phase difference detected by the phase difference detector in a normal mode, the first voltage controlled oscillator generating the first intermediate clock based on the input voltage held in the first voltage holding circuit in a holding mode;
a second voltage controlled oscillator that comprises a second voltage holding circuit holding an input voltage according to the phase difference, the second voltage controlled oscillator generating a second intermediate clock based on the input voltage according to the phase difference detected by the phase difference detector in the normal mode, the second voltage controlled oscillator generating the second intermediate clock based on the input voltage held in the second voltage holding circuit in the holding mode;
and
a selection circuit that selects one of the first and second intermediate clocks, and outputs the selected clock as an output clock and the feedback clock,
wherein the clock selected as the input clock is switched by the selector when the intermediate clock generated by the voltage controlled oscillator in the holding mode among the first and second intermediate clocks is output as the output clock and the intermediate clock generated by the voltage controlled oscillator in the normal mode is output as the feedback clock.

6 more elements

A control method of a phase locked loop circuit, the phase locked loop circuit comprising:

a selector that selects one of a plurality of clocks as an input clock;
a first frequency divider that divides a frequency of the input clock;
a second frequency divider that divides a frequency of a feedback clock;
a phase difference detector that detects a phase difference between the clock divided by the first frequency divider and the clock divided by the second frequency divider;
a first voltage controlled oscillator that comprises a first voltage holding circuit holding an input voltage according to the phase difference, the first voltage controlled oscillator generating a first intermediate clock based on the input voltage according to the phase difference detected by the phase difference detector in a normal mode, the first voltage controlled oscillator generating the first intermediate clock based on the input voltage held in the first voltage holding circuit in a holding mode;
a second voltage controlled oscillator that comprises a second voltage holding circuit holding an input voltage according to the phase difference, the second voltage controlled oscillator generating a second intermediate clock based on the input voltage according to the phase difference detected by the phase difference detector in the normal mode, the second voltage controlled oscillator generating the second intermediate clock based on the input voltage held in the second voltage holding circuit in the holding mode;
and
a selection circuit that selects one of the first and second intermediate clocks, and outputs the selected clock as an output clock and the feedback clock, the control method comprising:
outputting the intermediate clock generated by the voltage controlled oscillator in the holding mode among the first and second intermediate clocks as the output clock;
outputting the intermediate clock generated by the voltage controlled oscillator in the normal mode as the feedback clock;
and
switching the clock selected as the input clock by the selector.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/041,084Filed 4 Mar 2011
Priority: JP 2010-0489645 Mar 2010
Published: 8 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03L 7/08
Using a reference signal applied to a frequency- or phase-locked loop: details of the phase-locked loop
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…
H03L 7/0891
The phase or frequency detector generating up-down pulses: the up-down pulses controlling source and sink current generators, e.g. a charge pump
H03L 7/095
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using a lock detector