Digital noise filter
AssigneeRenesas Electronics Corporation
InventorRyoichi YAMAGUCHI
Life of this patent
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Abstract
A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.
Claims9
An apparatus comprising:
- a clock generating circuit that compares an input signal with an output signal to determine whether to generate a gating clock or not;
- and
- a noise filter circuit that operates based on said gating clock and monitors said input signal to determine whether to output said input signal as said output signal or not.
Dependencies are inferred from the claim text.