Clock generator circuits for generating clock signals

A circuit for generating a clock signal, the circuit comprising:

• a first current generator to generate a first mirror current;
• a first capacitor;
• a first transistor coupled between the first current generator and the first capacitor, the first transistor having a first threshold voltage VTH1 and including a gate to receive a first voltage V1 so as to allow the first mirror current to charge the first capacitor during a first half cycle;
• and
• a first discharging transistor to allow the first capacitor to discharge during a second half cycle,
• wherein the period of the first half cycle is proportional to the first bias voltage V1 minus the first threshold voltage VTH1.

A clock generator circuit comprising:

• a current source;
• and
• a first clock circuit coupled to the current source, the first clock circuit comprising:
• a first current generator comprising a first transistor and a second transistor,
• wherein a source of the first transistor is coupled to a power supply and a drain of the first transistor is coupled to a source of the second transistor;
• a third transistor of which a drain is coupled to a drain of the second transistor;
• a fourth transistor of which a drain is coupled to a source of the third transistor and a source is grounded;
• and
• a first capacitor of which a first end is coupled to the source of the third transistor and a second end is grounded.