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US 2011/0215836 A1Published application
Output buffer
AssigneeKabushiki Kaisha Toshiba
InventorYuui SHIMIZU
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor.
Claims21
An output buffer comprising:
- a clamp output stage configured to clamp a drain potential of a P-channel field effect transistor or a drain potential of an N-channel field effect transistor by inserting a field effect transistor for potential clamp in series between the P-channel field effect transistor and the N-channel field effect transistor and inputting an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor into a gate of the field effect transistor for potential clamp;
- and
- a data input part configured to be connected to the front of the clamp output stage and to input a data signal into a gate of the P-channel field effect transistor and a gate of the N-channel field effect transistor based on an enable signal during data output.
An output buffer comprising:
- a first clamp output part in which a first field effect transistor for potential clamp is inserted in series between a first P-channel field effect transistor and a first N-channel field effect transistor, an intermediate level between a high potential supplied to a source of the first P-channel field effect transistor and a low potential supplied to a source of the first N-channel field effect transistor is input into a gate of the first field effect transistor for potential clamp and a data signal is input into a gate of the first P-channel field effect transistor and a gate of the first N-channel field effect transistor;
- and
- a second clamp output part in which a second field effect transistor for potential clamp is inserted in series between a second P-channel field effect transistor and a second N-channel field effect transistor, an intermediate level between a high potential supplied to a source of the second P-channel field effect transistor and a low potential supplied to a source of the second N-channel field effect transistor is input into a gate of the second field effect transistor for potential clamp, and a data inversion signal which is inverted from the data signal is input into a gate of the second P-channel field effect transistor and a gate of the second N-channel field effect transistor.
An output buffer comprising:
- a first clamp output part configured to clamp a drain potential of a first P-channel field effect transistor or a drain potential of a first N-channel field effect transistor by inserting a first field effect transistor for potential clamp in series between the first P-channel field effect transistor and the first N-channel field effect transistor and inputting an intermediate level between a high potential supplied to a source of the first P-channel field effect transistor and a low potential supplied to a source of the first N-channel field effect transistor into a gate of the first field effect transistor for potential clamp;
- a second clamp output part configured to clamp a drain potential of a second P-channel field effect transistor or a drain potential of a second N-channel field effect transistor by inserting a second field effect transistor for potential clamp in series between the second P-channel field effect transistor and the second N-channel field effect transistor and inputting an intermediate level between a high potential supplied to a source of the second P-channel field effect transistor and a low potential supplied to a source of the second N-channel field effect transistor into a gate of the second field effect transistor for potential clamp;
- a first data input part configured to be connected to the front of the first clamp output part and to input a data signal into a gate of the first P-channel field effect transistor and a gate of the first N-channel field effect transistor based on an enable signal;
- and
- a second data input part configured to be connected to the front of the second clamp output part and to input a data inversion signal which is inverted from the data signal into a gate of the second P-channel field effect transistor and a gate of the second N-channel field effect transistor based on the enable signal.
2 more elements
An output buffer comprising:
- a first CMOS inverter;
- a second CMOS inverter;
- a first data input part configured to be connected to the front of the first CMOS inverter and to input a data signal into the first CMOS inverter based on an enable signal;
- a second data input part configured to be connected to the front of the second CMOS inverter and to input a data inversion signal which is inverted from the data signal into the second CMOS inverter based on an enable signal;
- and
- an input data deciding part configured to permit the data signal to be input into the first CMOS inverter and to permit the data inversion signal to be input into the second CMOS inverter only when the data signal changes.
3 more elements
An output buffer comprising:
- a first CMOS inverter;
- a second CMOS inverter;
- a first data input part configured to be connected to the front of the first CMOS inverter and to input a data signal into the first CMOS inverter based on an enable signal;
- a second data input part configured to be connected to the front of the second CMOS inverter and to input a data inversion signal which is inverted from the data signal into the second CMOS inverter based on an enable signal;
- and
- an output equalizing circuit configured to average an output level of the first CMOS inverter and an output level of the second CMOS inverter in synchronization with a clock signal.
3 more elements
Dependencies are inferred from the claim text.